1. Field of the Invention
Embodiments of the invention relate to the field of semiconductors, and more particularly, to semiconductor manufacturing or fabrication.
2. Description of Related Art
As the speed and density of semiconductor integrated circuits has increased, consequent thermal and electrical connectivity issues have raised the requirements for packaging. Typically, an integrated circuit die is mounted on a silicon building block, which in turn may be mounted on a plastic, or other material, substrate or package. This entire apparatus is then mounted on a printed circuit board.
Mounting to the printed circuit board generally involves a ball grid array or pin grid array and wiring to complete the electrical connection between the integrated circuit and the printed circuit board.
In particular, thermal and electrical connectivity issues have become increasingly important in the packaging realm in relation to graphics processing and dual central processing unit (CPU) systems.
For example, as to graphics processing, especially 3-D graphics processing, communication between a memory controller and an associated high-speed memory is required to be at very high speed and requires a great deal of bandwidth. Current configurations between a typical memory controller and a memory through a motherboard results in large latencies, and the overall large electrical parasitics restrict the electrical performance, and thus, current configurations are less than desirable for high speed 3-D graphics processing.
For example, with reference to FIG. 1A, a typical configuration is shown in which a memory controller 12 is connected through a motherboard 14 to a memory 16. As can be seen, this typical configuration utilizes a ball grid array 20 and wiring 23 to complete the electrical connections between the memory controller 12 and the memory 16 through the motherboard 14. Unfortunately, the latencies inherent in this type of configuration do not lend themselves to the high speed and large bandwidth requirements for intense 3-D graphics processing.
Similarly, for current dual CPU packages, an example of which is shown in FIG. 1B, the interconnect for the non-active CPU 40 or 42 may often show a stub effect when the other CPU 40 or 42 is active. This stub effect typically restricts the highest speed for the interconnection due to resonant phenomenon.
This type of typical configuration includes a first CPU 40, a second CPU 42, and an interconnect having a ball grid array 50 and wiring 51 to complete the electrical connections between the CPUs and through the package 55. Unfortunately, the stub effects between CPUs 40 and 42 impact the electrical performance significantly as input/output (I/O) speed increases.
As described above, typical packaging and mounting of dual die packages utilizing common ball grid arrays has become less desirable due to the increased need for high-speed electrical performance. One reason for this, as described above, is due to the long interconnections, causing high signal latency and therefore reducing operating frequency. Further, for dual die packages, using current packaging methods, overall manufacturing costs may be high due to wire bonding, molding, and other assembly tasks.